1. Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor memory apparatus having a sense amplifier.
2. Related Art
As the integration degree of a semiconductor memory apparatus increases, an area of each unit memory cell is reduced. As the area of each unit memory cell is reduced, attempts have been made to manufacture buried-type connection members (e.g., contact sections) for connecting switching elements, bit lines, word lines, and capacitors to one another.
At the present time, a unit cell area of a semiconductor memory apparatus is reduced from 8F2 (F is a minimum feature size) to 6F2, even further 4F2. Accordingly, it is also necessary to change a bit line structure for transmitting signals to a unit cell and an area of a sense amplifier for detecting and amplifying a bit line signal.
FIG. 1 is a schematic plan view illustrating a sense amplifier arrangement of a general 6F2 memory cell.
Referring to FIG. 1, a first mat MAT1 includes a plurality of bit lines BLn and BLn+1 and a second mat MAT2 includes a plurality of complementary bit lines /BLn and /BLn+1. The first mat MAT1 and the second mat MAT2 are spaced apart from each other by a predetermined interval in the extension direction of the bit lines, and the respective bit lines BL and complementary bit lines /BL are spaced apart from each other by the minimum feature size. As is well known in the art, since such a 6F2 structure has an open bit line structure, sense amplifiers S/An and S/An+1 between the mats MAT1 and MAT2 adjacent in the bit line direction are shared.
In more detail, the nth bit line BLn and the (n+1)th bit line BLn+1 of the first mat MAT1 are spaced apart from each other by the minimum feature size, and simultaneously the nth bit line BLn of the first mat MAT1 and the nth complementary bit line /BLn of the second mat MAT2 are also spaced apart from each other by the minimum feature size. Thus, the (n+1)th bit line BLn+1 and the nth complementary bit line /BLn are separate, but partially collinear.
The sense amplifiers S/An and S/An+1 are located between the nth bit line BLn of the first mat MAT1 and the nth complementary bit line /BLn of the second mat MAT2, and between the (n+1)th bit line BLn+1 of the first mat MAT1 and the (n+1)th complementary bit line /BLn+1 of the second mat MAT2, respectively. In this regard, the sense amplifiers are substantially located at one bit line pitch.
With such a structure, transistors constituting the latches of sense amplifiers S/An and S/An+1 need to be located at the distance d (i.e., the distance defined as the minimum feature size) between the bit line BL and the complementary bit line /BL, which form a pair.
Therefore, since the channel length of the transistor is equal to or less than the minimum feature size, the properties of the transistor may not be easily ensured, resulting in the reduction of the sensitivity of the sense amplifier.